1. Field of the Invention
The present invention relates to an image display apparatus in which crosstalk generated in a matrix-driven display panel is suppressed, and to a control method of the image display apparatus.
2. Description of the Related Art
Known flat panel displays (FPDs) include liquid crystal display devices (LCDs), plasma display devices (PDPs), organic EL display devices (OLEDs) and field emission display devices (FEDs).
Among the foregoing, FEDs have a passive matrix structure, i.e. a simple panel structure in which field emission elements are positioned at intersections of row wirings and column wirings. As a result, FEDs have characteristically a fast response at a low cost.
FIG. 2 is a basic configuration example of an ordinary matrix-driven image display apparatus (for instance, an FED). A plurality of column wirings 14 and a plurality of row wirings 15 are formed on a rear plate 16. Pixels (display elements) are formed at respective intersections of the column wirings 14 and the row wirings 15. The column wirings 14 are connected to a column drive circuit 12, and the row wirings 15 are connected to a row drive circuit 13, to make up thereby a display device module.
The image display apparatus of FIG. 2 comprises a control circuit 11 to which digital video image signals are inputted. The row drive circuit 13 is a circuit that applies a scan signal (selection voltage) to row wirings 15 that are to be driven, and that applies a non-selection voltage to other row wirings 15. The row wirings 15, for instance, are sequentially driven (scanned) one line at a time, from the top downwards. The column drive circuit 12 generates a driving waveform (modulation signal) for each column, on the basis of a driving row video image signal (luminance signal), and applies the generated driving waveforms to the respective column wirings 14. As a result, there can be outputted a desired video image through modulation of the luminance (electron emission amount of the electron-emitting device) of the display elements.
The trend towards ever greater size and higher definition in image display apparatuses translates into longer wirings and shorter distances between wirings. This entails greater wiring resistance and greater inter-wiring capacitance, and, accordingly, an increase in RC response time. Pixels that stand farther from the driving circuit (open end side) appear thereupon darker than pixels that stand closer to the driving circuit (driving end side). Technologies for correcting luminance variability include, for instance, technologies that involve correcting a video image signal using a correction value according to the position and gradation of a display element (U.S. Pat. No. 6,097,356), and technologies that involve correcting a video image signal in accordance with the rounding of a voltage signal through RC delay (Japanese Patent Application Laid-open No. H6-258614). The above technologies afford good correction of display defects in part of the display.
In display devices of active-matrix driving type, the distance between adjacent signal wirings (column wirings) and pixel electrodes in each pixel are small. As a result, crosstalk (poor image quality) occurs on account of capacitive coupling (transverse electric field). To deal with the above problem, technologies have been proposed in which a display signal of a pixel to be corrected is corrected on the basis of a display signal of the pixel to be corrected and display signals of adjacent pixels that influence the pixel to be corrected (Japanese Patent Application Laid-open No. 2006-23710).
However, although the technologies disclosed in U.S. Pat. No. 6,097,356 and Japanese Patent Application Laid-open No. H6-258614 allow satisfactorily correcting the position-dependant fixed unevenness of display elements, such technologies are ineffective on display defects caused by so-called crosstalk in which the degree of unevenness varies depending on the display image. Also, it has been found that some display defects remain uncorrected even when using technologies that involve correcting crosstalk on the basis of the display signal of an own pixel and display signals of adjacent pixels, as in Japanese Patent Application Laid-open No. 2006-23710.
For instance, a brightness gradient and/or chromaticity gradient may occur in the vertical direction in part of the video image pattern, as in FIG. 12A. Also, vertical streak (color) unevenness may occur in columns corresponding to the IC boundaries, as in FIG. 12B, in a case where the column drive circuit comprises a plurality of ICs and the column wirings are laid out in a pattern such as the one of FIG. 13.
Brightness may vary upon display of a display pattern such that the array is different even for a same gradation value. For instance, two patterns may be displayed, namely a checkered pattern of color units as in FIG. 14A, and a checkered pattern of white (RGB set) units, as in FIG. 14B. In this case, as illustrated in 14C, display is good at the driving end side in the vicinity of the column drive circuits, but the brightness of the two patterns are dissimilar at the open end side, and a brightness jump appears at the boundary between patterns.
As a result of diligent research, the inventors found that such phenomena arise from crosstalk caused by capacitive coupling between adjacent column wirings, in particular from the in-plane distribution of crosstalk.
This phenomenon will be explained based on FIG. 15. FIG. 15 is a simplified equivalent circuit of two column wirings. In the figure, Vn,0(t) is the output (voltage waveform), of a column drive circuit, that is applied to an n-th column wiring at a time t, and Vn,y(t) is the column wiring potential in the vicinity of a position y (y=1, 2, 3, 4). It is found that, since column wirings are ordinarily homogeneous, there holds C1≅C2≅C3≅C4≅Cy (constant), and R1≅R2≅R3≅R4≅Ry (constant), where Ry is the column wiring resistance per small interval at the position y, and Cy denotes the capacitance between adjacent wirings per small interval at the position y. When the modulation signals are dissimilar between the own pixel and pixels that are adjacent to the own pixel in the row direction (horizontal direction), the voltage between the ends of Cy changes at a time t, and there is generated, as a result, a current Iy such as the one given by Equation (1).
                              I          y                ≈                              C            y                    ⁢                                    ⅆ                              (                                                                            V                                                                        n                          -                          1                                                ,                        y                                                              ⁡                                          (                      t                      )                                                        -                                                            V                                              n                        ,                        y                                                              ⁡                                          (                      t                      )                                                                      )                                                    ⅆ              t                                                          (        1        )            
If Ry·Cy is small, Vn,y(t) is substantially constant and does not depend of the position y. Accordingly, Vn-1,y(t)−Vn,y(t) is likewise substantially constant and independent from the position y. Equation (1) implies that there holds I1≅I2≅I3≅I4≅Iy. Accordingly, the potential fluctuation (crosstalk) at the position y of the column wirings is determined by the cumulative value of IR drops of Iy and Ry from the driving end up to position y, as per Equation (2) to Equation (5). Here, Iy is the charge-discharge current of the capacitance between adjacent wirings Cy, and Ry is the column wiring resistance. That is, a display defect such as the one in FIG. 12A occurs on account of an IR drop derived from the column wiring resistance and the charge-discharge current of the capacitance between adjacent wirings on account of disparities between the modulation signals that are applied to adjacent column wirings. The IR drops are summated from the driving end side, and hence the crosstalk amount (IR drop) is larger at the open end. A brightness gradient such as that of FIG. 12A and/or color gradient occur(s) as a result.
                                          V                          n              ,              1                                ⁡                      (            t            )                          ≈                              ∑                          y              =              1                        4                    ⁢                      (                                          I                y                            ·                              R                y                                      )                          ≈                  4          ×                                    I              y                        ·                          R              y                                                          (        2        )                                                      V                          n              ,              2                                ⁡                      (            t            )                          ≈                                            V                              n                ,                1                                      ⁡                          (              t              )                                +                                    ∑                              y                =                2                            4                        ⁢                          (                                                I                  y                                ·                                  R                  y                                            )                                      ≈                  7          ×                                    I              y                        ·                          R              y                                                          (        3        )                                                      V                          n              ,              3                                ⁡                      (            t            )                          ≈                                            V                              n                ,                2                                      ⁡                          (              t              )                                +                                    ∑                              y                =                3                            4                        ⁢                          (                                                I                  y                                ·                                  R                  y                                            )                                      ≈                  9          ×                                    I              y                        ·                          R              y                                                          (        4        )                                                      V                          n              ,              4                                ⁡                      (            t            )                          ≈                                            V                              n                ,                3                                      ⁡                          (              t              )                                +                                    I              y                        ·                          R              y                                      ≈                  10          ×                                    I              y                        ·                          R              y                                                          (        5        )            
In ordinary large display devices, the column drive circuit comprises a plurality of ICs. Accordingly, the column wiring pattern in the panel is uniform and parallel in the display region, as illustrated in FIG. 13. Outside the display region, however, the leadout portions of the wirings are formed to a tapered shape, in order to connect the column wirings to the terminals of the ICs. Accordingly, the capacitance between adjacent wirings exhibits a nonuniform distribution outside the display region. In a column wiring at an IC boundary, for instance, the distance to another adjacent wiring on one side is greater than in other column wirings. Therefore, the capacitance between adjacent wirings outside the display region becomes about half that of other signal wirings. Using the model of FIG. 15 to account for this influence, an instance where C1≅0.5×Cy, for example, corresponds to a column wiring at an IC boundary, and an instance where C1≅Cy corresponds to an column wiring other than at the IC boundary. Such being the case, the potential fluctuations at the various positions of the column wirings corresponding to an IC boundary are given by Equations (6) to (9) below.
                                          V                          n              ,              1                                ⁡                      (            t            )                          ≈                                                            I                y                            ·                              R                y                                      2                    +                                    ∑                              y                =                2                            4                        ⁢                          (                                                I                  y                                ·                                  R                  y                                            )                                      ≈                  3.5          ×                                    I              y                        ·                          R              y                                                          (        6        )                                                      V                          n              ,              2                                ⁡                      (            t            )                          ≈                                            V                              n                ,                1                                      ⁡                          (              t              )                                +                                    ∑                              y                =                2                            4                        ⁢                          (                                                I                  y                                ·                                  R                  y                                            )                                      ≈                  6.5          ×                                    I              y                        ·                          R              y                                                          (        7        )                                                      V                          n              ,              3                                ⁡                      (            t            )                          ≈                                            V                              n                ,                2                                      ⁡                          (              t              )                                +                                    ∑                              y                =                3                            4                        ⁢                          (                                                I                  y                                ·                                  R                  y                                            )                                      ≈                  8.5          ×                                    I              y                        ·                          R              y                                                          (        8        )                                                      V                          n              ,              4                                ⁡                      (            t            )                          ≈                                            V                              n                ,                3                                      ⁡                          (              t              )                                +                                    I              y                        ·                          R              y                                      ≈                  9.5          ×                                    I              y                        ·                          R              y                                                          (        9        )            
The potential fluctuation at position 1 in a column wiring at an IC boundary is 3.5×Iy·Ry versus 4×Iy·Ry in the case of Equation (2). At positions 2, 3 and 4, the potential fluctuation varies uniformly by 0.5×Iy·Ry. That is, the distribution of capacitance between adjacent column wirings outside the display region is uniformly reflected on the distribution of the crosstalk amount of the respective lines. Vertical streak (color) unevenness such as that illustrated in FIG. 12B appears thus at columns corresponding to IC boundaries.
An example has been explained above in which the capacitance between adjacent column wirings outside the display region exhibits a distribution, but the same considerations apply also to a case where it is the wiring resistance outside the display region that exhibits a distribution. That is, both a disparity (distribution) in the wiring resistance (R) between column wirings outside the display region and other column wirings, and a disparity (distribution) in the capacitance between adjacent wirings (C) outside the display region can influence the distribution of crosstalk amount in the column direction (vertical direction).
The brightness jump illustrated in FIG. 14C occurs on account of the dissimilar crosstalk amount between column wirings in the pattern of FIG. 14A and the pattern of FIG. 14B. Focusing for instance on G column wirings, the adjacent R and B column wirings in the pattern of FIG. 14A are at a constant potential. In the pattern of FIG. 14B, by contrast, a modulation signal is applied to adjacent R and B column wirings. As a result, the crosstalk amount in G column wirings is dissimilar for the display patterns of FIG. 14A and FIG. 14B. Moreover, the brightness jump between the two patterns becomes ever more noticeable towards the open end, since the crosstalk amount increases towards the open end.
The correction method of Japanese Patent Application Laid-open No. 2006-23710 is aimed at crosstalk caused by local capacitive coupling and/or transverse electric field (or longitudinal electric field), i.e. is directed at phenomena in which there is no in-plane distribution of the crosstalk amount. Therefore, conventional correction methods are virtually ineffective when the distribution of crosstalk amount in the vertical direction (column direction) is large, as in the above-described problem, and/or when there is a left-right (row direction) distribution.